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Our Executive Team

Each Team Focuses Exclusively on single departments

Our team has working experience on RTL2GDS and Post silicon activities which helps any client to make things quicker in any stage of the project. You can walk along with the dedicated experienced engineering team and meet all the industry obligatory skill sets to accomplish any critical projects being with
Vaaluka.

Sunil Kumar Jasthi

- CEO & Founder

Mr. Sunil is a leader with exceptional technical skills in the area of VLSI design
verification of IPs, SoCs. During his 16+ years of engineering background and 8+ years of technical leadership, he worked for Ineda Systems (acquired by Intel), Cyient, IDT, Tundra Semiconductors. He has expertise in PCIe and virtualization extensions. He has handled verification of multiple PCIe designs (PCIe Endpoint, PCIe to PCI/x Bridge, PCIe Switch, Root Complex, and PCIe MR-IOV Switches). Sunil has experience in analyzing the issues found during validation of design on FPGA and emulation platforms; he has a complete understanding of Spec2GDS flow.

Dinesh Kumar Sabankar

- CTO & Co-Founder

Mr. Dinesh is a process-oriented engineering lead with 16+ years of experience in Design verification and defining methodologies. Prior to founding Vaaluka Solutions, he worked for Ineda Systems (acquired by Intel), Qualcomm, AMD, Xilinx, and Tundra Semiconductors. He has got exceptional automation skills which can make the process faster and optimal. His experience in creating robust environments makes him more special. He has been a key contributor for multiple PCIe products and ARM-based SoCs at various Tier 1 company

Suneetha Kanuga

- Engineering Director

Miss. Suneetha is a technical leader with 20+ years of experience in VLSI front-end verification. She worked for Xilinx, Cyient, IDT, Tundra Semiconductors, Alliance Semiconductors, Chip Engines, Sand Microelectronics and held different roles in both technical and management ladder. She served as Verification Prime for multiple PCIe-based products. She has experience in handling projects with teams spread in multiple geographical locations. She has managed and trained the teams with 10s of engineers.

Sunil Kumar Jasthi

- CEO & Founder

Dinesh Kumar Sabankar

- CTO & Co-Founder

Suneetha Kanuga

- Engineering Director

Mr. Sunil is a leader with exceptional technical skills in the area of VLSI design
verification of IPs, SoCs. During his 16+ years of engineering background and 8+ years of technical leadership, he worked for Ineda Systems (acquired by Intel), Cyient, IDT, Tundra Semiconductors. He has expertise in PCIe and virtualization extensions. He has handled verification of multiple PCIe designs (PCIe Endpoint, PCIe to PCI/x Bridge, PCIe Switch, Root Complex, and PCIe MR-IOV Switches). Sunil has experience in analyzing the issues found during validation of design on FPGA and emulation platforms; he has a complete understanding of Spec2GDS flow.

Mr. Dinesh is a process-oriented engineering lead with 16+ years of experience in Design verification and defining methodologies. Prior to founding Vaaluka Solutions, he worked for Ineda Systems (acquired by Intel), Qualcomm, AMD, Xilinx, and Tundra Semiconductors. He has got exceptional automation skills which can make the process faster and optimal. His experience in creating robust environments makes him more special. He has been a key contributor for multiple PCIe products and ARM-based SoCs at various Tier 1 company

Miss. Suneetha is a technical leader with 20+ years of experience in VLSI front-end verification. She worked for Xilinx, Cyient, IDT, Tundra Semiconductors, Alliance Semiconductors, Chip Engines, Sand Microelectronics and held different roles in both technical and management ladder. She served as Verification Prime for multiple PCIe-based products. She has experience in handling projects with teams spread in multiple geographical locations. She has managed and trained the teams with 10s of engineers.

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Front end Design, Verification, Validation

Our team has extensive hands-on experience on different EDA tools of Cadence, Mentor, Synopsys both with standard and customized flows. We have a team with the capability to build the flow based on the customer requirementsr

Physical Design

Our team has extensive hands-on experience on different EDA tools of Cadence, Mentor, Synopsys both with standard and customized flows. We have a team with the capability to build the flow based on the customer requirementsr

Embedded Software

We have strong Embedded Software development skills and has expertise in Linux and Peta Linux operating Systems Team has proficiency in Embedded C, C++ & Scripting languages (Python/shell/TCL/Perl)


About us

Built over with zeal and having a good base in the area of Design Verification by a process-oriented and passionate team who has got 16+ years of industrial experience and 8+ years of managerial experience which can plan and lead a project.

Expertise

Our core team has a very sound understanding of the system specification. We have expertise from architectural design and implementation to functional verification and validation.


Executive team

Our team has working experience on RTL2GDS and Post silicon activities which helps any client to make things quicker in any stage of the project. We provide ingenious solutions beyond the customer enclosure.


Join us & Excel in your Professional Career with us

Job ID: VS – DE21050900100

Job Title: RTL Design Enginee

Job Description: 

Role and Responsibilities:

  • Proficiency in Verilog/VHDL, System Verilog, C/TCL
  • Experience in any High speed bus interfaces (PCIe/Ethernet/USB) or high bandwidth memory (DDR4/HBM) based IP development is a plus
  • Experience in Xilinx Vivado/ISE tool knowledge and understanding of timing and implementation reports
  • Debug expertise with Xilinx Chipscope (ILA) and Lecroy
  • AMBA AXI, PCIe protocol and Cache expertise is a plus

Job Deliverable:

  • Design Specification creation from Requirement Document
  •  RTL coding in Verilog/System Verilog
  • Lint/CDC runs, report reviews, and analysis
  • IP level simulations and debug
  • Vivado Synthesis, implementation, and timing reviews
  • FPGA Validation and debug with Chipscope
  • Writing Validation test cases in C/tcl

Level of Experience:

  •  1 to 6 years of experience
  •  BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

                Location: Hyderabad

Job ID: VS – VE21050900101

Job Title: RTL Verification Engineer

Job Description: 

Role and Responsibilities:

  • Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM
  • Previous work experience with High-Speed Serial Protocols (PCIe/USB/Ethernet) or DDR verification with knowledge of AXI
  • Experience in analyzing Code and Functional Coverage
  • Modifying test cases to meet Coverage goals
  • Experience in debugging the regression failures
  • Knowledge of any one scripting language Perl/python/shell
  • AMBA AXI, PCIe protocol, and Cache expertise is a plus

Level of Experience:

  •  1 to 6 years of experience
  •  BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

                Location: Hyderabad/Bangalore

Job ID:VS PD21050900102

Job Title: Physical Design Engineer

Role and Responsibilities:

  • Responsible for Physical Design from Netlist to GDS2 for blocks at the 7nm technology node.

Tool Expertise Required:

  • Hands on experience in ICC2 or Innovus
  • Good control over scripting languages like PERL, TCL and strong debug capabilities
  • Ability to debug/workaround and make progress is a must.
  • Hands-on experience with physical verification tools is beneficial

Level of Experience:

  • 3 to 5 years of experience
  • BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

Location: Hyderabad/Bangalore

Delivered Turnkey Project for Fortune 100 listed company

Worked as part of the offshore team for a Tier1 customer l.

Working with a Fortune 800 listed company

Association of 450+ manmonths service in T & M Model

Worked as Offshore team for Malaysia based Tier1 Client

Delivered at an onsite location (Malaysia) for a Tier1 customer.

Worked as Offshore team for US based Client

Regression cleanup of test cases across 5 platforms[Near 500 test scenarios]

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Contact Details

Phone Numbers​

+91 9885453480

Email

support@vaalukasolutions.com

Address​

Flat No 101, 102, 1st Floor, RVS SREE HOMES, Maata Bhuwaneswari Society SY No: 51 & 54, Hitech City Main Rd, Khanammet, Telangana 500081

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